The present invention relates to a semiconductor device and more particularly to a semiconductor memory device using a silicon on insulator (SOI) substrate. The present invention also relates to a manufacturing method of the semiconductor device.
The SOI substrate in which an insulation film (buried insulation film) is provided on a silicon substrate and a silicon layer is provided on the insulation film has been known in, for example, Japanese Patent Application Laid-Open Publication No. 2001-298171 and Japanese Patent Application Laid-Open Publication No. 5-257356(1993).
A semiconductor memory device having a floating body cell (FBC) memory cell with a portion corresponding to a channel region of MOS transistor formed in the silicon layer on the buried insulation film of such an SOI substrate used as a floating body so as to accumulate electric charges has been developed.
In such a semiconductor memory device, the area of its memory cell can be extremely reduced because a capacitor may be eliminated, so that high integration can be achieved and accordingly the memory capacity per unit area can be increased.
In the FBC, as far as SOI film thickness concerned, as the degree of depleted condition is intensified to full depleted (FD) condition, namely, the thinner the SOI film be, the higher ΔVth which can serve as a criterion when detecting information accumulated in the memory cell may be increased. This ΔVth indicates a difference between Vth when “0” data is stored and Vth when “1” data is stored.
Because this FD condition is easier to be obtained as the thickness of the SOI film is decreased, the thickness of the SOI film is required to be decreased as much as possible from viewpoints of improvement (increase of ΔVth) of the performance of the memory cell of the FBC cell.
Furthermore, the BOX film which is buried oxide film is preferred to be as thin as possible in order to improve coupling between the body and a substrate electrode (hereinafter referred to a plate electrode) of the memory cell. Therefore, both of the buried oxide film and the SOI film thereon are preferred to be as thin as possible.
However, manufacturing of a SOI wafer with the BOX film set to less than 60 Angstrom in thickness and the SOI film set to less than 300 Angstrom in the SOI substrate requires highly accurate control of wafer manufacturing process, thereby leading to increase in wafer manufacturing cost, which is a large obstacle to achievement of an excellent FBC.
If the thickness of the SOI film is too small, when a contact is formed, not only electric short-circuit is likely to occur between the contact and plate potential but also contact resistance is increased, which is a problem to be solved. Although the SOI film can be thinned uniformly, if the SOI film is thinned to about 20 nm, the ΔVth is decreased, so that an intention of improving performance using a device under a fully depleted condition by thinning the SOI film is not achieved.
Additionally, if the BOX film is thinned extremely, diffusion capacitance increases so that sharing of process with a logic section, which is a large advantage of the FBC, becomes impossible.